1. Architecture
    1. Network-on-Chip
    2. Static Random Access Memory
    3. Unpacker
    4. Computation Engine
    5. Packer
    6. RISC-V Cores
  2. Internal Registers
  3. Kernels
  4. Circular Buffers

Hey, I am Niro, a new PhD student! My PhD revolves around molecular dynamics simulation and hardware produced by a company called Tenstorrent. It is a US-based company, which produces computers with focus on AI/ML and HPC. In this blog post, I am going to introduce the major component of their hardware, called Tensix Core. This post is inspired by a presentation I gave internally at FZJ. All figures I use are own representations based on the TT-Metal guide1.

JSC is freshly hosting two Tenstorrent Galaxy Blackhole servers2. A total of 32 Tenstorrent Blackhole ASICs are integrated within a single server. Each accelerator chip contains 130 Tensix Cores - next to other components. Like with other accelerated devices, we call the hosting CPU-based system the host, and a Blackhole ASIC a device.

Architecture

I am going to explain the architecture134 of a Tensix Core in a bottom-up approach. It contains two Network-on-Chip interfaces, Static RAM, an Unpacker, a Matrix engine, a Vector engine and a Packer.

Network-on-Chip

Tensix Core: Network on Chip

Each Tensix Core has two Network-on-Chip (NoC) interfaces to communicate with other Tensix Cores or the DRAM. A Tensix Core is placed on a board that implements the NoC architecture5. All Tensix Cores exchange packets through network components (switch, router or Ethernet). Based on the chosen network component, only certain layers of the OSI reference model6 have to be implemented. One should distinguish between hardware and software level. Both NoC are able to receive and send packets on hardware level, however as a software convention the first NoC interface is used to receive packets and the second interface is used to send packets. The actual data and the necessary headers are part of the packet. The headers have to be removed from or added to the data, for which the Unpacker and Packer units are used, respectively.

Static Random Access Memory

Tensix Core: Static Random Access Memory

Packets are stored temporarily in the local memory of a Tensix Core, which is a Static RAM (SRAM) of size 1.5 MB. The main data type used is a Tensor. It stores multidimensional arrays. Tenstorrent hardware are designed to work with so-called tiles7. A tile is a grid of data words aligned in 32 rows and 32 columns. All entries of the grid have the same data type. A tensor can consist of multiple tiles. In case one dimension of a tile is not a multiple of 32, zeros are padded to the end of the tile. Usually, the host processor starting the computation works in row-major data formats8. Thus, a transformation from row-major format to the tile format is required. This process is called tilization; the reverse is called untilization. Tiles are not directly stored in the SRAM. First, a tile is split into four so-called faces. A face is a grid of 16 rows and 16 columns. It is stored in row-major format one after another in the SRAM.

Tenstorrent’s TT-Metalium (TT-Metal) offers two ways to execute the transformation, on the host or on the device. The first one has to be executed prior working with the device.

Unpacker

Tensix Core: Unpacker

Before starting the actual computation process on the Tensix Core, the packets have to be unpacked for the subsequent computational units to work with the actual data. Each core contains an Unpacker unit. The tilization of a tensor can be executed in this unit.

Computation Engine

A Tensix Core contains two computing engines9, the Special Function Processing Unit (SFPU) and the Function Processing Unit (FPU). The SFPU is a vector engine, while the FPU uses matrix operations. There is a trade-off between throughput and precision within the engines1011. While the SFPU has a higher precision, it can handle less data. The vector engine operates with 32 bits (FP32), and can execute also complex functions. The matrix engine operations on 19 bit data, supporting data precision formats, which require less or equal 19 bits: FP8, FP16, BFLOAT16, BLOCKFP2, BLOCKFP4, BLOCKFP8 and TF32. This engine handles simple, but massively parallel operations.

Tensix Core: engines

The following gives an overview of possible operations from the a machine learning view (the exact functions offered by TT-Metal are not listed here).

SFPU
  • operations
    • basic arithmetic
    • integer
    • comparision and logical
    • bitwise
  • quantization
  • data manipulation and processing
  • initilization and utilies
  • functions
    • exponential and logical
    • rounding and ceiling
    • hyberbolic
    • special mathematical
    • trigonometric
    • activation
FPU
  • elementwise
    • mulitplication
    • addition
    • subtraction
    • pooling

Packer

The result of the engines are given to the Packer unit, to pack the data and – if required – perform untilization.

RISC-V Cores

Tensix Core: RISC-V CPUs

To drive the units, (un)packers and NoC interfaces, Tenstorrent implements five so-called baby RISC-V cores. The cores implement the RISC-V32IM12 13 ISA (32 bit base architecture with additional instructions for integer multiplication and division). Each RISC-V core gives the commands to the corresponding unit in the Tensix Core. Two RISC-V cores (data movement core 0 and data movement core 1) are placed before the NoC interfaces, while the remaining RISC-V cores (unpack core, math core and pack core) are placed in the computation part (Unpacker, Matrix engine, Vector engine and Packer).

Tensix Computation: Registers

Internal Registers

Each Tensix Core contains additional registers to store data temporarily, which are used by the computation part of the Tensix Core8. Two registers (SrcA, SrcB) are placed inside the FPU. They hold the input of the current matrix operation. The SFPU only contains one register (LReg), which is used to store intermediate results during vector operations. The Dst register has two usages. For a matrix operation, it stores the result so the Packer can retrieve it. For a vector operation, it stores the input as well as the output.

Tensix Computation: Matrix operation

The flow of a matrix operation is the following. The Unpacker retrieves the inputs from the SRAM and places them into the SrcA and SrcB registers. After finishing the operation, the matrix engine writes the result to the Dst register. The Packer retrieves the result and places into the SRAM.

For vector operations, it’s similar: The Unpacker retrieves the inputs and places them into the Dst register. The vector retrieves the inputs from the Dst register. If needed, temporary results are stored in the LReg register. The result is stored in the Dst register. The Packer retrieves the result and places into the SRAM. Tensix Computation: Vector operation

Also both computations – matrix and vector operations – can happen at the same time.

Kernels

Typically, it’s required to implement three kernels to control the RISC-V cores8: a reader kernel or data movement kernel, a writer kernel or another data movement kernel, and a computation kernel. The benefit of separating kernels is to reuse kernels for other Tensix Cores.

Tensix Core: kernels

Circular Buffers

A software-based Circular Buffer14 (CB) is used for communication between pairs of kernels1 (reader-computation and computation-writer). These buffers are allocated in the local memory. The device allows 32 buffers in total to be allocated. For each input, a buffer is assigned and used between the reader and computation kernel. The output of a computation is stored in one CB and is used by the computation and writer kernel. Each CB is capable of storing at least two tiles. TT-Metal offers an API to implement these buffers15.

Currently, Tenstorrent offers two processors, Wormhole1617 and Blackhole1819. Each processors contains a different number of Tensix Cores. These processors are built into PCIe boards. The concrete number of Tensix Core can vary between different PCIe boards. In addition, the Blackhole adds SiFive x280 RISC-V cores to the card.

  1. TT Architecture and Metalium Guide, https://github.com/tenstorrent/tt-metal/blob/main/METALIUM_GUIDE.md ↩ ↩2 ↩3

  2. Tenstorrent Galaxy, https://tenstorrent.com/hardware/galaxy ↩

  3. Almerol, Jenny L., Boella, Elisabetta, Spera, Mario, and Gregori, Daniele. 2025. “Accelerating Gravitational N-Body Simulations Using the RISC-V-Based Tenstorrent Wormhole.” In Proceedings of the SC ‘25 Workshops of the International Conference for High Performance Computing, Networking, Storage and Analysis (SC Workshops ‘25). Association for Computing Machinery, New York, NY, USA, 1729–1735, https://doi.org/10.1145/3731599.3767528 ↩

  4. Brown, Nick and Barton, Ryan. 2025. “Accelerating stencils on the Tenstorrent Grayskull RISC-V accelerator.” In Proceedings of the SC ‘24 Workshops of the International Conference on High Performance Computing, Network, Storage, and Analysis (SC-W ‘24). IEEE Press, 1690–1700, https://doi.org/10.1109/SCW63240.2024.00211 ↩

  5. Kumar, Sashi, Jantsch, Axel, Soininen, Juha-Pekka, Forsell, Martti, Millberg, Mikael, Öberg, Johnny, Tiensyrjä, Kari, Hemani, Ahmded, “A network on chip architecture and design methodology,” Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002, Pittsburgh, PA, USA, 2002, pp. 117-124, https://doi.org/10.1109/ISVLSI.2002.1016885 ↩

  6. Day, John D. and Zimmermann, Hubert, “The OSI reference model,” in Proceedings of the IEEE, vol. 71, no. 12, pp. 1334-1340, Dec. 1983, https://doi.org/10.1109/PROC.1983.12775 ↩

  7. Tiles, https://docs.tenstorrent.com/tt-metal/latest/tt-metalium/tt_metal/advanced_topics/tiles.html ↩

  8. Scott, Michael L., Programming language pragmatics. Morgan Kaufmann, pp. 335-337, 2009. ↩ ↩2 ↩3

  9. Computer Engines and Data Flow within Tensix, https://docs.tenstorrent.com/tt-metal/latest/tt-metalium/tt_metal/advanced_topics/compute_engines_and_dataflow_within_tensix.html, ↩

  10. Achieving FP32 Accuracy for Computation, https://docs.tenstorrent.com/tt-metal/latest/tt-metalium/tt_metal/advanced_topics/fp32_accuracy.html ↩

  11. Tensix Coprocessor, https://github.com/tenstorrent/tt-isa-documentation/blob/main/WormholeB0/TensixTile/TensixCoprocessor/README.md ↩

  12. 2.1 RV32I Base Integer Instruction Set, Version 2.1, https://docs.riscv.org/reference/isa/unpriv/rv32.html ↩

  13. 12.1 “M” Extension for Integer Multiplication and Division, Version 2.0, https://docs.riscv.org/reference/isa/unpriv/m-st-ext.html ↩

  14. Barbour, Ahmed E. and Alhayek, Iyad, “A parallel, high speed circular queue structure,” Proceedings of the 32nd Midwest Symposium on Circuits and Systems, Champaign, IL, USA, 1989, pp. 1089-1092 vol.2, https://doi.org/10.1109/MWSCAS.1989.102043 ↩

  15. Circular Buffer APIs, https://docs.tenstorrent.com/tt-metal/latest/tt-metalium/tt_metal/apis/kernel_apis/circular_buffers/circular_buffers.html ↩

  16. Wormhole, https://tenstorrent.com/hardware/wormhole ↩

  17. Specifications and Requirements (Wormhole:tm:), https://docs.tenstorrent.com/aibs/wormhole/specifications.html ↩

  18. Blackhole, https://tenstorrent.com/hardware/blackhole ↩

  19. Specifications and Requirements (Blackhole:tm:), https://docs.tenstorrent.com/aibs/blackhole/specifications.html ↩