DARE: European RISC-V Ecosystem for Future Supercomputers
Since last year, we have been involved in DARE SGA1. DARE is a EuroHPC project that sets out to build a fully European supercomputing stack for HPC and AI, featuring high-performance and energy-efficient RISC-V processors designed and developed in Europe and an integrated, high-performing software stack. In this blog post, I’d like to share some updates on our activities in the first year of the project.
About DARE
DARE (Digital Autonomy with RISC-V in Europe) drives the development of cutting-edge chiplet processors for HPC. The project utilizes the developments of other projects, like EPI and EUPILOT, to ensure secure, efficient, and scalable computing solutions tailored to European needs and building up on open technology.
As a critical part of this effort, DARE also focuses on the software/hardware co-design process, where real software requirements are used to guide the hardware design, and early information from the hardware partners is used to ensure that the software stack is ready for when the hardware is available.
Our role in the Project
JSC participates in the DARE project with two roles: First, we are leading the Software Technical Area, maintaining an overview of the software ecosystem being developed and using our expertise in HPC to help guide both software and hardware development. Second, we also contribute to the development of optimized software components like BLAS and FFT libraries as well as Kokkos.
Software Technical Area
One of the challenges in DARE is to develop software and provide co-design feedback to the hardware partners when the hardware is not yet available. In that past year, we have worked on different methods to address this challenge, and come up with a promising strategy using hardware emulators and comparison to state of the art hardware, drawing on our experience with other emerging architectures that we have dealt with in the past in our Accelerating Devices lab.
Hardware-Specific Optimized Libraries
Efficient scientific computing depends heavily on optimized numerical libraries.
In DARE, we contribute to this area through projects such as blisgen,
ukrgen, and juFFTe. blisgen focuses on generating optimized BLIS
micro-kernels for different vector architectures, including RISC-V Vector, ARM
NEON/SVE, and AVX2/AVX512, while ukrgen explores systematic generation and
evaluation of low-level micro-kernel implementations across architectures.
To complement this LA-focused effort, we are working on juFFTe1, which is a FFT library
that supports FFT kernel generation and optimization strategies for emerging
architectures, while still trying to be reasonably lightweight. Together, these projects support the development and evaluation
of optimized DGEMM, SGEMM, and FFT building blocks, while also providing
insight into how core numerical kernels can be adapted to future RISC-V-based
HPC systems.
Beyond these software developments, we are also studying the maturity and performance characteristics of the emerging RISC-V ecosystem for HPC. This includes evaluating processors, software stacks, development tools, and architectural features such as the RISC-V Vector Extension (RVV) using representative scientific workloads and benchmark suites. These studies help identify both opportunities and remaining challenges for RISC-V adoption in HPC, providing valuable insights for hardware/software co-design and helping inform decisions for future European supercomputer architectures.
Bringing Kokkos to DARE Architectures
Kokkos has become one of the most widely-used performance-portability frameworks in HPC, with many applications at JSC relying on it to target a wide range of CPU and accelerator architectures through a common programming model. As part of DARE, we are working to ensure that Kokkos runs correctly and efficiently on emerging RISC-V platforms. We continuously run the Kokkos test suite on our RISC-V testbed hardware, investigate failures, and contribute fixes and improvements upstream to the Kokkos project.
Software Stack and Continuous Integration
For new architectures to become usable, software must be built, tested, and validated continuously across different systems. JSC contributes to the broader DARE software stack by supporting continuous integration efforts based on the exaCB and Easybuild frameworks.
Looking Ahead
In the first year of the DARE project, we have now set up a base of hardware optimized libraries and software infrastructure which other partners can use to test and evaluate the emerging RISC-V ecosystem. We have also developed co-design methods with our hardware partners to establish feedback mechanisms that are not only useful for our current project, but can also form a blueprint of how to effectively co-design software and hardware for future hardware as well. And our library developments mature constantly.
Further Reading
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At ISC26, we’ll show the performance of juFFTe and publish the library on Github. ↩